1. Field of the Invention
The present invention relates generally to amplifier circuits, and more particularly, the present invention relates to an amplifier circuit that delays a signal.
A claim of priority is made to Korean Patent Application No. 2003-29761 filed May 12, 2003 and No. 2003-87990 filed Dec. 5, 2003 in the Korean Patent Office. Both disclosures are hereby incorporated by reference in their entirety.
2. Description of the Related Art
In general, amplifier circuits receive an input signal, amplify the input signal by a predetermined factor, and thereafter output a resulting amplified signal. A typical, conventional amplifier circuit is shown in FIG. 1. Referring to FIG. 1, a differential amplifier 10 includes load PMOS transistors PM1 and PM2, differential NMOS transistors NM1 and NM2, and a current source NMOS transistor NM3. Differential amplifier 10 outputs an output signal OUT having some predetermined delay with respect to input signals IN and INB. In other words, it takes some predetermined period of time for the output signal OUT to appear at a voltage node NOD once input signals IN and INB are respectively applied to the gates of differential NMOS transistors NM1 and NM2. Since conventional amplifier circuits produce an output signal that is delayed with respect to a corresponding input signal due to the propagation delays inherent in conduction of the signal through the amplifier circuit components, such circuit are often specifically used as delay circuits. However, conventional amplifier circuits are characterized by a fixed delay, and are accordingly difficult to use in circuits requiring a variable or variably controlled delay.
For data transmission between semiconductor memory devices and memory controllers, for example, an input/output (I/O) interface method is conventionally used in which data is transmitted in synchronization with a clock signal having a predetermined frequency. In the context of this I/O interface method, it has become increasingly important to achieve accurate temporal synchronization between the clock signal and data output events. This accurate timing requirement will continue to be an issue as bus transfers and data transmission speeds increase. Thus, in order for data output to be accurately synchronized to a prescribed clock edge or the center of a data output period, the clock signal provided to relevant circuit components must be temporally adjusted (e.g., delayed) in relation to other delays affecting the output of data, such as, for example, the delay inherent in the transfer of data onto a databus. Thus, semiconductor memory devices typically include an internal clock generator that receives an external clock signal and generates an internal clock signal. The internal clock generator may be implemented by a phase locked loop (PLL) or a delay locked loop (DLL). An internal clock generator implemented using a DLL circuit is shown in FIG. 2.
More particularly, FIG. 2 is a block diagram of a conventional internal clock generator and a data output circuit of the type typically included in a semiconductor memory device.
Referring to FIG. 2, an internal clock generator 20 receives an external clock signal EXCLK and generates an internal clock signal INCLK3. A data output circuit 30 outputs DATA read from a memory core (not shown) to an external device in synchronization with internal clock signal INCLK3, as generated by internal clock generator 20. Internal clock generator 20 includes a variable delay circuit 40, a buffer circuit 50, a replica delay circuit 60, and a phase detector 70. The data output circuit 30 includes an internal output circuit 31 and an output driver 32. Buffer circuit 50 includes a duty correction unit 51 and a clock buffer circuit 52. Clock buffer circuit 52 includes a first buffer unit 53 and a second buffer unit 54.
It is desirable that the replica delay circuit 60 be configured to have a delay that is equal a time period required to output the DATA via data output circuit 30. However, it is difficult to configure replica delay circuit 60 such that the delay provided by replica delay circuit 60 is equal to the delay period associated with data output circuit 30. Thus, the delay provided by replica delay circuit 60 is usually not equal to the delay associated with data output circuit 30. As a result, the internal clock signal INCLK3 generated by internal clock generator 20 is not synchronized with the external clock signal EXCLK even after delay adjustments by a phase-locked or delay-locked circuit. Some phase offset usually remains.
Thus, in a conventional internal clock generator, a buffer circuit providing an additional delay adjustment is used to compensate for the phase offset of an internal clock signal. The composition and operation of this circuit is further illustrated with reference to FIGS. 3A and 3B.
FIG. 3A is a schematic diagram illustrating first buffer unit 53 of FIG. 2 in some additional detail. Similarly, FIG. 3B is a schematic diagram illustrating second buffer unit 54 of FIG. 2 in some additional detail.
Referring to FIG. 3A, first buffer unit 53 includes buffers 81 through 83. Referring to FIG. 3B, second buffer unit 54 includes buffers 91 through 93. Here, buffers 81 through 83 and the buffers 91 through 93 are implemented using substantially identical circuits.
Referring to FIG. 3B, a first plurality of capacitors C1 through C3 is connected in parallel, each with one node connected between the buffers 91 and 92, and a second plurality of capacitors C4 through C6 is connected in parallel, each with one node between the buffers 92 and 93. Capacitors C1 through C3 delay a signal output from buffer 91 for a predetermined time. Capacitors C4 through C6 similarly delay a signal output from buffer 92. Thus, the total delay provided by second buffer unit 54 depends on capacitances of capacitors C1 through C6.
As described above, conventional internal clock generator 20 compensates for the phase offset of internal clock signal INCLK3 by varying the capacitances of the capacitors C1 through C6 in clock buffer circuit 52. However, such a conventional configuration has several problems.
First, in order to provide variable delay adjustments, clock buffer circuit 52 should include variable capacitances. Second, if data output circuit 30 is heavily loaded, then the capacitors used in clock buffer circuit 52 must have large capacitance. Third, since the first and second pluralities of capacitors, C1 through C6, included in the clock buffer circuit 52 can only delay internal clock signal INCLK1, as opposed to accelerating the clock signal, it is difficult to finely adjust the phase offset of internal clock signal INCLK3.
Where the first and second pluralities of capacitors, C1 through C6, are included in the second buffer unit 54 of clock buffer circuit 52, as shown in FIG. 3B, the duty cycle of the internal clock signal INCLK3 output from second buffer unit 54 changes. However, since first buffer unit 53 doesn't similarly include the delaying capacitor structures , the internal clock signal INCLK2 output from first buffer unit 53 and the internal clock signal INCLK3 output from second buffer unit 54 have different duty cycles.